Digital Backend Engineer

Who we are

Move Silicon is the business unit of Move S.p.A. focused on the development of high-efficiency ASIC and SoC solutions for industrial, automotive, and IoT applications. We work closely with global customers to bring innovative analog and mixed-signal devices to market, with a strong emphasis on reliability, scalability, and sustainable engineering practices.

The role

We are building a new team of highly skilled engineers to tackle the most challenging aspects of digital backend implementation, with a strong focus on technical excellence and innovation.

We are looking for a Digital Backend Engineer with solid experience in the physical implementation (RTL-to-GDSII) of complex ASICs and SoCs. The selected candidate will join the Digital Design team and will primarily work on the implementation and production deployment of advanced eFPGA IP architectures.

Previous experience in the eFPGA domain is considered a strong plus.

In addition to implementation activities, the engineer will contribute to the development, enhancement, and maintenance of internal backend design flows and automation methodologies.

Key responsibilities

• RTL-to-GDSII implementation flow for ASIC and eFPGA IP architectures
• Synthesis and floorplanning, including macro placement, channel definition, and power grid architecture
• Place-and-Route using Cadence Innovus, Synopsys ICC2/Fusion Compiler, or Siemens Aprisa, with focus on congestion, timing, and DRC closure
• Clock Tree Synthesis (CTS) and optimization of skew, jitter, and insertion delay
• Static Timing Analysis (STA) using PrimeTime or Tempus, including setup/hold closure across multi-corner and multi-mode scenarios
• Power integrity and IR-drop analysis, including integration of low-power methodologies (UPF, DVFS, power gating)
• Physical verification and sign-off activities (DRC/LVS, EM/IR) using Calibre or Pegasus
• Development and maintenance of automation scripts in TCL, Python, and Bash for backend flows and regression environments
• Continuous improvement of internal physical design methodologies and implementation flows
• Preparation of technical documentation and status reports for digital designers, layout teams, and management
• Mentoring junior engineers and interfacing with foundries, packaging, and test service providers

Requirements

Must-have

• 4–5 years of experience in ASIC or SoC backend/physical design
• MSc degree in Electronic Engineering, Computer Engineering, or equivalent
• Strong knowledge of Innovus/ICC2/Aprisa and PrimeTime/Tempus
• Expertise in CTS, STA, DRC/LVS, and multi-corner timing closure
• Scripting skills in TCL/Python and familiarity with Git
• Solid understanding of physical implementation methodologies from RTL to GDSII

Nice-to-have

• Previous experience with eFPGA architectures and implementation flows
• Experience with FinFET technology nodes ≤ 7nm
• Advanced low-power implementation techniques (UPF, active clock gating)
• EM/IR sign-off experience (Voltus, RedHawk)
• High-speed IP integration experience (PCIe, DDR, SerDes)
• Knowledge of ISO 26262 / AEC-Q100 automotive requirements

What we offer

• Permanent contract under the Italian CCNL Commercio agreement
• Gross annual salary of €38–53k, based on experience
• Competitive compensation package including meal vouchers and annual performance bonus
• Dynamic and innovation-driven environment with continuous learning opportunities (EDA training, conferences such as DATE and ISPD)
• Opportunity to work on advanced eFPGA technologies and next-generation semiconductor products
• Exposure to cutting-edge process nodes from 180nm to 5nm and beyond
• Offices located in the heart of Milan and Lucca, close to public transportation and services
• Flexible smart working policy
• Health insurance and additional employee benefits
• Team-building activities and regular company events

Work locations

Via Marcantonio Colonna 35, 20149 Milan, Italy – hybrid working available.
Via Carlo Piaggia 421, 55100 Lucca, Italy – hybrid working available.

How to apply

Please send your updated CV to careers@move-x.it with the subject line “Digital Backend Engineer – Physical Design & Sign-off”.
Only candidates meeting the mandatory requirements will be considered.

Move Silicon is an equal opportunity employer. We welcome applications regardless of gender, sexual orientation, ethnicity, age, disability, or personal beliefs.

Applicants of all genders are encouraged to apply in accordance with Italian Law 903/77. Please refer to our GDPR privacy policy pursuant to Article 13 of EU Regulation 2016/679.

Chi siamo

Move Silicon è la business unit di Move S.p.A. dedicata allo sviluppo di soluzioni ASIC e SoC ad alta efficienza per applicazioni industriali, automotive e IoT. Lavoriamo in stretta collaborazione con clienti globali per portare sul mercato dispositivi analogici e mixed-signal innovativi, con un forte focus sull’affidabilità e sulla sostenibilità dei nostri progetti.

La posizione

Stiamo costruendo un nuovo team di ingegneri altamente qualificati per affrontare le sfide più complesse sul digital backend, con un focus sull’innovazione e sull’eccellenza tecnica.

Cerchiamo a tale scopo un/una Digital Backend Engineer con solida esperienza nella progettazione fisica (RTL-to-GDSII) di ASIC/SoC complessi. La figura sarà responsabile di floor-planning, place-&-route, timing closure e verifiche di sign-off, assicurando che i nostri dispositivi rispettino gli obiettivi di prestazioni, area e potenza prima del tape-out.

Responsabilità principali

• Synthesis e floor-planning a partire da netlist RTL, definendo macro placement, channel e power grid.
• Place-&-Route (Cadence Innovus, Synopsys ICC2/ Fusion Compiler, Siemens Aprisa) con focus su congestione, timing e DRC.
• Clock-Tree Synthesis (CTS) e ottimizzazione di skew, jitter e insertion delay.
• Static Timing Analysis (STA) con PrimeTime o Tempus, chiusura di hold/set-up e path criticali multi-corner.
• Power e IR-drop analysis, integrazione di tecniche low-power (UPF, DVFS, power gating).
• Physical verification (DRC/LVS), EM/IR e sign-off di layout con Calibre o Pegasus.
• Script di automazione (TCL, Python, Bash) per flussi P&R e regressioni di verifica su server farm.
• Generazione di documentazione tecnica e report di stato per designer digitali, layout e management.
• Mentorship di profili junior e interfaccia con foundry e service house di package & test.

Requisiti

Must-have

4-5 anni di esperienza in backend/physical design ASIC o SoC

Laurea magistrale in Ingegneria Elettronica/Informatica (o equivalente)

Padronanza di Innovus/ICC2/Aprisa e PrimeTime/Tempus

Competenze di CTS, STA, DRC/LVS e chiusura timing multi-corner

Capacità di scripting in TCL/Python e uso di Git

Nice-to-have

Esperienza su nodi FinFET ≤ 7 nm

Implementazioni low-power avanzate (UPF, active clock gating)

Sign-off EMIR (Voltus, RedHawk)

Integrazione IP ad alta velocità (PCIe, DDR, SerDes)

Conoscenza requisiti ISO 26262/AEC-Q100 per automotive

Cosa offriamo

• Economics: tempo indeterminato CCNL Commercio RAL 38-53K (in base all'esperienza) + buoni pasto elettronici.
• Crescita: ambiente dinamico che favorisce innovazione e formazione continua (corsi tool EDA, conferenze DATE/ISPD).
• Sede: uffici nel cuore di Milano e Lucca, vicino a trasporti pubblici e servizi.
• Socialità: team-building ed eventi regolari per rafforzare lo spirito di squadra.
• Benefit: bonus annuale legato ai risultati, mensa interna/buoni pasto, assicurazione sanitaria.

Sede di lavoro

Via Marcantonio Colonna 35, 20149 Milano – possibilità di smart working.

Via Carlo Piaggia 421, 55100 Lucca – possibilità di smart working.

Come candidarsi

Invia CV aggiornato a careers@move-x.it indicando nell’oggetto “Digital Backend Engineer – Physical Design & Sign-off”. Saranno presi in considerazione solo i profili che soddisfano i requisiti must-have.

Move Silicon promuove le pari opportunità: accogliamo candidature senza distinzione di genere, orientamento, etnia o convinzioni personali.

Accogliamo candidati di ogni genere (ai sensi della Legge 903/77). Ti invitiamo a leggere la nostra informativa sulla privacy, art. 13 del regolamento (UE) 2016/679 sulla protezione dei dati (GDPR).